Index
I-14 ADSP-214xx SHARC Processor Hardware Reference
internal memory (continued)
DMA modifier (IDP_DMA_Mx)
registers, 11-20, 11-21
DMA modifier (IMSPx) registers, 2-5,
2-25
internal serial clock, setting, 10-29, 10-30
internal vs. external frame syncs, 10-18
interpolation, FIR filter, 6-39
interrputs
chained, 2-46
interrupt
enable interrupt on error (INTERR) bit,
15-26
interrupt and timer pins, 23-30
interrupt controller, DAI, 9-32
interrupts
accelerator, 6-64
channel priority, 2-48
conditions for generating interrupts,
10-46
data transfer, starting, 11-30
digital applications interface, 9-33
DMA slave, 4-19
(enable RX status interrupt) bit, A-247
exception, 9-32
external memory booting, 3-89
FFT, 6-18
FFT accelerator, 6-18
FIFO to memory, 11-29
latch (IRPTL) register, 15-26
latch/mask (LIRPTL) registers, 15-26
link ports, 4-16
MAC status, FIR, 6-65
masking, 2-45
masking and latching, 4-20
peripheral timers, 16-18
polling, 2-45
priority, 2-48
interrupts (continued)
priority interrupt control registers
(PICR), B-4
restrictions, B-3
SPORTs, 10-49
SRC, 12-16
status, fir, 6-45
system, 9-32
transfer completion, 2-46
vector, sharing, 10-50
INVFSx (active low frame sync select for
frame sync) bits, 14-13
I/O interface to peripheral devices, 10-1
I/O processor, 2-24
address bus (IOA), 2-25
and addressing,
2-25
bu
ffer, 2-36
DMA data, 2-32
bus priority, 2-42
bus priority, external port, 2-43, A-20,
A-46
bus structure, 2-30
chain assignment, 2-33
chained DMA, 2-11
chain pointer (CPSPI) register, 2-11
chain pointer registers, 2-7
configuring DMA, 2-51
count registers, 2-6, 2-27
DMA channel registers, 2-36
IDP buffer, 2-10
miscellaneous external port parameter
registers, 2-9
standard (non chained) DMA, 2-23
TCB memory allocation, 2-32
transfer types, 2-1, 2-2
ISSS (input service select) bit, A-242
K
kernel boot timing, 23-23
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