DMA Channel Registers
2-6 ADSP-214xx SHARC Processor Hardware Reference
Count registers. These registers, shown in Table 2-4, indicate the number
of words remaining to be transferred to or from memory on the corre-
sponding DMA channel.
IMIIR 16 Accelerator IIR data input
CMIIR 16 Accelerator IIR coeff input
OMIIR 16 Accelerator IIR output
IMFFT 16 Accelerator FFT input
OMFFT 16 Accelerator FFT output
IMMTMW 16 MTM Write
IMMTMR 16 MTM Read
IMEP0–1 16 External Port
EMEP0–1 27 External Port (external)
Table 2-4. Count Registers
Register Name Width (Bits) Description
ICSP0–7A 16 SPORTA
ICSP0–7B 16 SPORTB
ICSPI 16 SPI
ICSPIB 16 SPIB
IDP_DMA_C0–7 16 IDP
ICLB0–1 16 Link Port
CUART0RX 16 UART0 Receiver
CUART0TX 16 UART0 Transmitter
ICFIR 16 Accelerator FIR data input
CCFIR 16 Accelerator FIR coeff input
OCFIR 16 Accelerator FIR output
Table 2-3. Modify Registers (Cont’d)
Register Name Width (Bits) Description
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