Peripheral Registers
A-108 ADSP-214xx SHARC Processor Hardware Reference
Channel Status Configuration Registers
(MLB_CSCRx)
This register, shown in Figure A-50 and described in Table A-68, shows
the status of the current and previous buffer for the given logical channel.
For all bits a 1 means the condition exists.
Figure A-50. MLB_CECRx Register
STS (0)
Current Buffer Protocol Error
BM
GIRB
Generate Break
RDY
Next Buffer Ready
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
BF
Channel x Buffer Empty
Channel x Buffer Full
STS (1)
Current Buffer Detect Break
STS (2)
Receive Service Request (I/O)
Current Buffer Done (DMA)
STS (3)
Transmit Service Request (I/O)
Current Buffer Start (DMA)
STS (4)
Buffer Error
STS (5)
Host Bus Error
STS (6)
Lost Frame Sync
STS (8)
Transmit Service Request (I/O)
Receive Packet Abort (DMA)
STS (9)
Receive Packet Start (I/O)
Previous Buffer Detect Break (DMA)
STS (10)
Reserved (I/O)
Previous Buffer Done (DMA)
STS (11)
Reserved (I/O)
Previous Buffer Start (DMA)
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