ADSP-214xx SHARC Processor Hardware Reference 15-27
Serial Peripheral Interface Ports
2. The
SPIEN control bit in SPICTL is cleared, disabling the SPI
system.
3. The MME status bit in SPISTAT is set.
4. An SPI interrupt is generated.
These four conditions persist until the MME bit is cleared by a write
1-to-clear (W1C-type) software operation. Until the MME bit is cleared, the
SPI cannot be re-enabled, even as a slave. Hardware prevents the program
from setting either SPIEN or SPIMS while MME is set.
When MME is cleared, the interrupt is deactivated. Before attempting to
re-enable the SPI as a master, the state of the SPI_DS_I input pin should
be checked to ensure that it is high; otherwise, once SPIEN and SPIMS are
set, another mode-fault error condition will immediately occur. The state
of the input pin is reflected in the input slave select status bit (bit 7) in the
SPIFLG register.
As a result of SPIEN and SPIMS being cleared, the SPI data and clock pin
drivers (MOSI, MISO, and SPICLK) are disabled. However, the slave-select
output pins revert to control by the processor flag I/O module registers.
This may cause contention on the slave-select lines if these lines are still
being driven by the processor.
Debug Features
The following sections provide information on features that help in
debugging SPI software.
Shadow Receive Buffers
A pair of read-only (RO) shadow registers for the receive data buffers,
RXSPI and RXSPIB are available for use in debugging software. These regis-
ters,
RXSPI_SHADOW and RXSPIB_SHADOW, are located at different addresses
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