ADSP-214xx SHARC Processor Hardware Reference 10-11
Serial Ports
• “Data Types and Companding” on page 10-12
• “Frame Sync” on page 10-16
Architecture
A serial port receives serial data on one of its bidirectional serial data sig-
nals configured as inputs, or transmits serial data on the bidirectional
serial data signals configured as outputs. It can receive or transmit on both
channels simultaneously and unidirectionally, where the pair of data sig-
nals can both be configured as either transmitters or receivers.
The SPORTx_DA and SPORTx_DB channel data signals on each SPORT can-
not transmit and receive data simultaneously for full-duplex operation.
Two SPORTs must be combined to achieve full-duplex operation. The
SPTRAN bit in the SPCTLx register controls the direction for both the A and
B channel signals.
The data direction of channel A and channel B on a particular
SPORT must be the same.
Serial communications are synchronized to a clock signal. Every data bit
must be accompanied by a clock pulse. Each serial port can generate or
receive its own clock signal (SPORTx_CLK). Internally-generated serial clock
frequencies are configured in the DIVx registers. The A and B channel data
signals shift data based on the rate of
SPORTx_CLK.
In addition to the serial clock signal, data may be signaled by a frame syn-
chronization signal. The framing signal can occur at the beginning of an
individual word or at the beginning of a block of words. The configura-
tion of frame sync signals depends upon the type of serial device
connected to the processor. Each serial port can generate or receive its own
frame sync signal (
SPORTx_FS) for transmitting or receiving data. Inter-
nally-generated frame sync frequencies are configured in the
DIVx
registers. Both the A and B channel data signals shift data based on their
corresponding
SPORTx_FS signal.
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