Programming Model
10-60 ADSP-214xx SHARC Processor Hardware Reference
In the ADSP-214xx processors the FSED bit in the SPCTLN register
allows SPORT initialization regardless of the state of the external
frame sync. The SPORT starts the transfer on the next valid edge.
Companding As a Function
Since the values in the transmit and receive buffers are actually com-
panded in place, the companding hardware can be used without
transmitting (or receiving) any data, for example during testing or debug-
ging. This operation requires one peripheral clock cycle of overhead, as
described below. For companding to execute properly, program the
SPORT registers prior to loading data values into the SPORT buffers.
To compress data in place without transmitting use the following
procedure.
1. Set the SPTRAN bit to 1 in the SPCTLx register. The SPEN_A and
SPEN_B bits should be = 0.
2. Enable companding in the DTYPE field of the SPCTLx transmit con-
trol register.
3. Write a 32-bit data word to the transmit buffer. Companding is
calculated in this cycle.
4. Wait two cycles. Any instruction not accessing the transmit buffer
can be used to cause this delay. This allows the serial port com-
panding hardware to reload the transmit buffer with the
companded value.
5. Read the 8-bit compressed value from the transmit buffer.
To expand data in place, use the same sequence of operations with the
receive buffer instead of the transmit buffer. When expanding data in this
way, set the appropriate serial word length (SLEN) in the SPCTLx register.
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