Analog Devices SHARC ADSP-214 Series User Manual

Effect Latency
17-8 ADSP-214xx SHARC Processor Hardware Reference
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Shift Register Effect Latency
After the SR register is configured, the maximum effect latency is 2 PCLK
cycles.
Programming Model
Since the SR_CTL, SRU_CLK_SHREG, and SRU_DAT_SHREG register signals
come from the peripheral clock domain (PCLK) to the SR_SDCLK_I and
SR_LAT_I domain, there are timing violations for one SR_SCLK_I period.
To avoid this program the folloing registers in the order listed.
1. The
SRU_CLK_SHREG, and SRU_DAT_SHREG registers.
2. The SR_CTL register.
3. Drive the SR_SDCLK_I, SR_LAT_I, and SR_SDI_I input signals.
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Analog Devices SHARC ADSP-214 Series Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-214 Series
Category	Computer Hardware
Language	English