FFT Accelerator
6-26 ADSP-214xx SHARC Processor Hardware Reference
Horizontal FFT Configuration
13.Once the last DMA in Step 10 completes, configure a coefficient
DMA to read 2H twiddle factors from the horizontal coeff buffer
into the accelerator.
14.Once the DMA in Step 12 completes, configure a data DMA
(chained or via interrupt) to read 2N – 1 data points from special
buffer into the accelerator with a modify value = 2V and a circular
buffer length of 2N – 1. Chain a data DMA of count = 1 that reads
the last imaginary point.
15.Configure a data DMA to write 2N–1 data points from the acceler-
ator into the output buffer with a modify value = 2V and a circular
buffer length of 2N – 1. There is no need to wait until the DMA in
Step 9 completes. Chain a data DMA of count = 1 that reads the
last imaginary point.
16.Wait until the DMA in step 14 completes (by interrupt or polling).
The computed FFT is now in the output buffer and the accelerator
is in idle mode.
N >= 512, Repeat
For details on the storage format of the coefficients see “Internal Memory
Storage” on page 6-8.
Transmit DMAs take place using input TCBs; receive DMAs take
place using output TCBs.
1. Configure the
ACCSEL bits in the PMCTL1 register to select the FFT
accelerator.
2. Factor N = VH, where 16 ≤ V and 16 ≤ H.
3. Set (=1) the FFT_RST bit in the FFTCTL1 register and wait for a min-
imum of 4 CCLK cycles.
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