ADSP-214xx SHARC Processor Hardware Reference 12-9
Asynchronous Sample Rate Converter
ratios, two SRCs may have differences in their ratios from 0 to 4
SRCx_FS_OP period counts. The (SRCx_FS_OP)/(SRCx_FS_IP) ratio adjusts
the filter length of the SRC, which corresponds directly with the group
delay. Thus, the magnitude in the phase difference depends upon the res-
olution of the SRCx_FS_OP and SRCx_FS_IP counters. The greater the
resolution of the counters, the smaller the phase difference error.
Serial Data Ports
The serial data ports provide the interface through which data is trans-
ferred into and out of the SRC modules.
The SRC has a 3-wire interface for the serial input and output ports that
supports left-justified, I
2
S, and right-justified (16-, 18-, 20-, 24-bit)
modes. Additionally, the serial interfaces support TDM mode for
daisy-chaining multiple SRCs to a processor. The serial output data is
dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data
is selected.
The SRC converts the data from the serial input port to the sample rate of
the serial output port. The sample rate at the serial input port can be asyn-
chronous with respect to the output sample rate of the output serial port.
Operating Modes
The SRC can operate in TDM, I
2
S, left-justified, right-justified, and
bypass modes. The serial ports of the processor can be used for moving the
SRC data to/from the internal memory.
In I
2
S, left-justified and right-justified modes, the SRCs operate individu-
ally. The serial data provided in the input port is converted to the sample
rate of the output port. Figure 12-3 shows the timing in the various
formats.
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