Functional Description
12-8 ADSP-214xx SHARC Processor Hardware Reference
rate, a fast mode has been added to the filter. When the digital-servo loop
starts up or the sample rate is changed, the digital-servo loop kicks into
fast mode to adjust and settle on the new sample rate. Upon sensing the
digital-servo loop settling down to some reasonable value, the digital-servo
loop kicks into normal or slow mode. During fast mode, the
SRCx_MUTE_OUT bit of the SRC is asserted to remind the user to mute the
SRC which avoids clicks and pops.
The FIR filter is a 64-tap filter in the case of SRCx_FS_OP < SRCx_FS_IP
and is (SRCx_FS_IP)/(SRCx_FS_OP) × 64 taps for the case when
SRCx_FS_IP > SRCx_FS_OP. The FIR filter performs its convolution by
loading in the starting address of the RAM address pointer and the ROM
address pointer from the digital-servo loop at the start of the SRCx_FS_OP
period. The FIR filter then steps through the RAM by decrementing its
address by 1 for each tap, and the ROM pointer increments its address by
the (SRCx_FS_OP/SRCx_FS_IP) × 2
20
ratio for SRCx_FS_IP > SRCx_FS_OP or
2
20
for SRCx_FS_OP < SRCx_FS_IP. Once the ROM address rolls over, the
convolution is complete. The convolution is performed for both the left
and right channels, and the multiply/accumulate circuit used for the con-
volution is shared between the channels.
The (SRCx_FS_IP)/(SRCx_FS_OP) sample rate ratio circuit is used to dynam-
ically alter the coefficients in the ROM for the case when
SRCx_FS_IP > SRCx_FS_OP. The ratio is calculated by comparing the out-
put of an SRCx_FS_OP counter to the output of an SRCx_FS_IP counter. If
SRCx_FS_OP > SRCx_FS_IP, the ratio is held at one. If SRCx_FS_IP >
SRCx_FS_OP, the sample rate ratio is updated if it is different by more than
two SRCx_FS_OP periods from the previous SRCx_FS_OP to SRCx_FS_IP
comparison. This is done to provide some hysteresis to prevent the filter
length from oscillating and causing distortion.
However, the hysteresis of the (SRCx_FS_OP)/(SRCx_FS_IP) ratio circuit can
cause phase mismatching between two SRCs operating with the same
input and output clocks. Since the hysteresis requires a difference of more
than two SRCx_FS_OP periods to update the SRCx_FS_OP and SRCx_FS_IP
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