ADSP-214xx SHARC Processor Hardware Reference 13-19
Sony/Philips Digital Interface
External Analog PLL
Notice there are various performance characteristics to consider when con-
figuring for analog PLL mode. In order to provide the receiver with an
external PLL the appropriate routings needs to be performed including the
setting of DIR_PLLDIS bit which disables the internal PLL and connects to
the external PLL. For more information about using PLLs, visit the Ana-
log Devices Inc. web site at: http://www.analog.com/en/
clock-and-timing/pll-synthesizersvcos/products/index.html
Interrupts
All S/PDIF interrupts are generated by the transmitter and receiver and
processed through the DAI interrupt controller which can generate an
interrupt signal using the (DAI_IMASK_x) registers.
Table 13-6 provides an overview of S/PDIF interrupts.
Transmitter Interrupt
The DIT_BLKSTART_O output signal, if routed to any miscellaneous inter-
rupt bits (
DAI_INT_31–22 in the SRU_MISCx register), triggers a block start
interrupt during the last frame of current block.
Table 13-6. S/PDIF Interrupt Overview
Interrupt Source Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
DAI S/PDIF
RX/TX (I2S, left/right
justified, TDM, 2
channels)
– TX block start
– RX audio status (no
audio, status change,
emphasis)
– RX error (lock, valid-
ity, no stream, biphase,
parity, CRC)
Read-to-clear
DAI_IRPTL_x
+ RTI instruction
P0I, P12I
(S/PDIF RX
only)
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