ADSP-214xx SHARC Processor Hardware Reference 10-59
Serial Ports
Programming Packed Mode
Since packed mode is implemented on top of multichannel mode, pro-
gramming this mode is the same as programming multichannel mode. Use
the serial port control (SPCTLx) and channel selection registers (SPMCTLx)
to configure the serial ports to run in packed mode as follows.
1. Configure the multichannel channel select registers.
2. Set the OPMODE, ICLK, IFS, CKRE bits in the SPCTLx register to run in
packed master mode.
3. Clear the LSBF bit to run in packed mode.
4. To emulate I
2
S in packed mode, set the MFD bit field to one and the
NCH bit field according to the channels in the SPMCTLx register.
The MFD bit field and the L_FIRST bit allow programs to manipulate the
timing as follows.
1. The MFD bit field selects the data delay in SCLK cycles after the frame
sync occurred.
2. The L_FIRST bit allows to swap the left and right channels.
Additional Information for External
Frame Sync Operation
There are two procedures which allow programs to save SPORT initializa-
tion during an inactive frame sync:
• Read the
DAI_PIN_STAT register of the frame sync to get the level
prior to starting SPORT configuration.
•Route a MISCA register input to the external frame signal (rising or
falling edge) as an interrupt trigger to generate an interrupt to start
SPORT configuration.
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