Data Transfers
15-20 ADSP-214xx SHARC Processor Hardware Reference
•If
GM = 0 and the receive buffer is full, the incoming data is
discarded, and the RXSPI register is not updated.
2. If core access to a SPI master is unable to keep up with the trans-
mit/receive stream during a transfer operation (because of an
interrupt or another reason) the SPI stalls the SPICLK until new
data is read/written into the TXSPI/RXSPI buffers. In this scenario
the ROVF/TUVF condition bits are set indicating an exception in the
data stream.
DMA Buffer Status
If the DMA engine is unable to keep up with the transmit/receive stream
during a transfer operation because of latency caused by using multiple
DMA channels, the SPI operates according to the states of the SENDZ and
GM bits in the SPICTLx register.
•If SENDZ = 1 and the transmit buffer is empty, the device repeatedly
transmits zeros on the MOSI pin. One word is transmitted for each
new transfer initiate command.
•If SENDZ = 0 and the transmit buffer is empty, the device repeatedly
transmits the last word transmitted before the transmit buffer
became empty.
•If
GM = 1 and the receive buffer is full, the device continues to
receive new data from the
MISO pin, overwriting the older data in
the
RXSPI buffer.
•If GM = 0 and the receive buffer is full, the incoming data is dis-
carded, and the RXSPI register is not updated.
Core Transfers
The RXS bit defines when the receive buffer can be read. The TXS bit
defines when the transmit buffer can be filled. The end of a single word
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