Data Transfer
11-20 ADSP-214xx SHARC Processor Hardware Reference
DMA Channel Priority
When more than one channel has data ready, the channels always access
the
IDP_FIFO register with fixed priority, from low to high channel num-
ber (that is, channel 0 is the highest priority and channel 7 is the lowest
priority). For the I/O processor, the eight DMA channels are considered
as a group and arbitration can rotate across groups for system balance. For
more information, see “Rotating DMA Channel Arbitration” on
page 2-44.
Standard DMA
The eight DMA channels each have a set of registers for standard DMA:
an I-register, an M-register and a C-register are used.
The IDP DMA parameter registers have these functions:
• Internal index registers (IDP_DMA_Ix). Index registers provide an
internal memory address, acting as a pointer to the next internal
memory location where data is to be written.
• Internal modify registers (IDP_DMA_Mx). Modify registers provide
the signed increment by which the DMA controller post-modifies
the corresponding internal memory Index register after each DMA
write.
• Count registers (
IDP_DMA_Cx). Count registers indicate the number
of words remaining to be transferred to internal memory on the
corresponding DMA channel.
This DMA access is enabled when the IDP_EN bit and IDP_DMA_EN bit and
the IDP_DMA_ENx bits register are set to select a particular channel. The
DMA is performed according to the parameters set in the various DMA
registers and IDP control registers. An interrupt is generated after end of
DMA transfer (when the count = 0).
To Next Page
Loading...
Need help?
General
