ADSP-214xx SHARC Processor Hardware Reference 12-11
Asynchronous Sample Rate Converter
TDM Input Daisy Chain
In TDM input port, several SRCs can be daisy-chained together and con-
nected to the serial input port of a SHARC processor or other processor
(Figure 12-4). The SRC IP contains a 64-bit parallel load shift register.
When the
SRCx_FS_IP_I pulse arrives, each SRC parallel loads its left and
right data into the 64-bit shift register. The input to the shift register is
connected to SRCx_DATA_IP_I, while the output is connected to
SRCx_TDM_IP_O. By connecting the SRCx_TDM_IP_O to the SRCx_DATA_IP_I
of the next SRC, a large shift register is created, which is clocked by
SRCx_CLK_IP_I.
The number of SRCs that can be daisy-chained together is limited
by the maximum frequency of SRCx_CLK_xx_I, refer datasheet for
exact value. For example, if the maximum frequency of
SRCx_CLK_xx_I is X MHz, and the output sample rate is fS, then
number of SRCs (n) that can be connected in daisy chained fashion
is: n × 64 × fs <= X MHz.
TDM Output Daisy Chain
In TDM output port, several SRCs can be daisy-chained together and
connected to the SPORT of an ADSP-214xx or other processor
(Figure 12-4). The SRC OP contains a 64-bit parallel load shift register.
When the SRCx_FS_OP_I pulse arrives, each SRC loads its left and right
data into the 64-bit shift register. The input to the shift register is con-
nected to
SRCx_TDM_OP_I, and the output is connected to SRCx_DAT_OP_O.
By connecting the
SRCx_DAT_OP_O to the SRCx_TDM_OP_I of the next SRC,
a large shift register is created, which is clocked by SRCx_CLK_OP_I.
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