Operation Modes
10-34 ADSP-214xx SHARC Processor Hardware Reference
Figure 10-8 shows an example of timing for a multichannel transfer with
SPORT pairing using SPORT0 and 1. The transfer has the following
characteristics.
• SPORT1–0 have the same
SCLK and frame sync as input.
• Multichannel is configured as 8 channels.
• SPORT0A drives data to DAC1 during slot 1–0 which asserts TDV
for 2 slots.
• SPORT1A drives data to DAC2 during slot 3–2 which asserts TDV
for 2 slots.
• SPORT1B receives data from ADC during slot 3–0.
Transmit Data Valid Output
In the ADSP-214xx processors, each SPORT has its own transmit data
valid output signal (
SPORTx_TDV_0) which is active during the transmission
of an enabled word. Because the serial port’s receiver signals are
Figure 10-8. Multichannel Operation
SPORT1
-
0_CLK_I
SLOT0 THREE-STATESLOT1
SLOT2THREE-STATE SLOT3
SLOT2 SLOT3SLOT0 SLOT1
SPORT1
-
0_FS_I
SPORT0_TDV_O
SPORT0_DA_I
SPORT1_TDV_O
SPORT1_DA_O
SPORT1_DB_I
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