ADSP-214xx SHARC Processor Hardware Reference 3-3
External Port
• Arbitration Logic to coordinate core, SPORT DMA, external port
DMA, transfers between internal and external memory over the
external port.
• External port supports various ratios of core to external port clock
determined by programming bits in the power management con-
trol registers (
PMCTL). For more information, see
“ADSP-2147x/ADSP-2148x Power Management Registers” on
page A-12.
Pin Descriptions
For the external port pin descriptions of the AMI and SDRAM/DDR2
interfaces, see the appropriate processor-specific data sheet.
Pin Multiplexing
The address, data and memory select pins are multiplexed for the AMI
and the SDRAM controller but not for the DDR2 controller. For more
information on multiplexing schemes refer to “Pin Multiplexing” on
page 23-28.
Register Overview
This section provides brief descriptions of the major registers. For com-
plete register information, see Appendix A, Registers Reference.
AMI Control Registers (AMICTLx). These registers control the mode of
operations for the four banks of external memory. Note for all AMI tim-
ing bit settings, all defined cycles are derived from the SDRAM clock.
AMI Status Register (AMISTAT). This 32-bit register provides status
information for the AMI interface and can be read at any time.
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