Features
5-2 ADSP-214xx SHARC Processor Hardware Reference
Features
The memory-to-memory port incorporates:
• 2 DMA channels (read and write)
• Internal to internal transfers
• Data engine for DTCP applications (only for special part numbers)
Note that the SHARC supports another internal to internal DMA module
(external port) which does support multiples DMA modes.
Register Overview
MTM control register (MTMCTL). Enables the read and write DMA
channels across the internal memory and returns status about the read or
write DMA channel.
Clocking
The fundamental timing clock of the MTM is peripheral clock (PCLK).
Boot Capable No
Local Memory No
Clock Operation f
PCLK
Table 5-1. MTM Port Specifications (Cont’d)
Feature Availability
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