ADSP-214xx SHARC Processor Hardware Reference 11-19
Input Data Port
DMA Transfers
The processors support two types of DMA transfers, standard and
ping-pong. Eight dedicated DMA channels can sort and transfer the data
into one buffer per source channel. When the memory buffer is full, the
DMA channel raises an interrupt in the DAI interrupt controller.
Data Buffer Format for DMA
The LSB bits 2–0 of the data format from the serial inputs are channel
encoding bits. Since the data is placed into a separate buffer for each
DMA channel (defined by parameter index registers), these bits are not
required and are cleared (=0) when transferring data to internal memory
through the DMA. However, bit 3 still contains the left/right status infor-
mation. In the case of PDAP data or 32-bit I
2
S and left-justified modes,
these three bits are a part of the 32-bit data.
For serial input channels, data is received in an alternating fashion from
left and right channels. Data is not pushed into the FIFO as a full
left/right frame. Rather, data is transferred as alternating left/right words
as it is received. For the PDAP and 32-bit (non-audio) serial input, data is
transferred as packed 32-bit words.
Figure 11-9. IDP Data Buffer Formats for the PDAP
24 7
010
0
31
0
BA
ABC
ABCD
NO PACKING
1x20-BIT
12 0
A
RESERVED
8
PACKING BY 2
2x16-BIT
PACKING BY 3
TRI-WORD
PACKING BY 4
4x8-BIT
31
31
31 151623
11
16 15
21 20
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