ADSP-214xx SHARC Processor Hardware Reference 3-115
External Port
Access Completion
This is the default mode of interrupt generation where the DMA complete
interrupt is generated when accesses are completed.
• For external write DMA, the DMA complete interrupt is generated
only after external writes on the DMA external interface are done.
• For external read DMA, the DMA complete interrupt is generated
when the internal DMA writes complete.
In this mode, the DMA interface can be disabled as soon as the interrupt
is received, (there is no need to check
EXTS before disabling the DMA
interface).
The DMA interface can be disabled based on a DMA complete
interrupt. However, the external device interfaces—AMI/SDRAM
may still be performing writes of the DMA data. Prior to disabling
any of these devices, programs should check their respective status
bits.
Internal Transfer Completion
This mode of interrupt generation is enabled when INTIRT bit is set in the
DMA control register. This mode of interrupt generation resembles tradi-
tional SHARC DMA interrupt generation and is provided for backward
compatibility. This interrupt is generated once the DMA internal transfers
(transmit or receive) are completed. For external transmit DMA, there
may be still external access pending at the external DMA interface when
the completion interrupt is generated. Therefore, the DMA may be dis-
abled on the DMA complete interrupt only if the external interface is idle
(for example, EXTS = 0).
Interrupt Dependency on DMA Mode
Interrupt generation varies, depending on the DMA mode used. The
INTIRT bit determines whether the interrupt is generated on internal
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