FIR Accelerator
6-28 ADSP-214xx SHARC Processor Hardware Reference
Read from Local Memory
1. Enable FFT module using the PMCTL1 register.
2. Wait at least 4 CCLK cycles.
3. Clear the FFT_DMAEN bit in the FFTCTL1 register.
4. Set the FFT_DBG bit in the FFTCTL1 register.
5. Write address to the FFTDADDR register. The MSB address bits
determine which memory to read.
6. Wait at least 20 CCLK cycles before writing data to FFTDDATA
register.
FIR Accelerator
Finite Impulse Response (FIR) filters are used in a wide array of applica-
tions, and can be used in multi-rate processing in conjunction with an
interpolator or decimator.
Features
This hardware module is capable of performing FIR filters without core
intervention. This gives programs freedom to use the core to implement
complex algorithms, effectively adding more bandwidth to the processor.
• FIR supports fixed point and IEEE floating point format
• Single rate or multi-rate window processing
• Change the rates with decimation or interpolation mode
• Up to 32 filter channels available
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