Features
7-2 ADSP-214xx SHARC Processor Hardware Reference
Features
The following is a brief summary of the features of this interface.
• Four independent PWM units
• 2-phase output timing unit
• Center or edge aligned PWM
• Single or double update PWM timer period
• Output logic allows redirection of 2-phase output timing
• PWM units can operate synchronized to each other
• Complementary outputs allows bridge based applications
A block diagram of the module is shown in Figure 7-1. The generation of
the four output PWM signals on pins AH to BL is controlled by four pri-
mary blocks.
• The two-phase PWM timing unit, which is the core of the PWM
controller, generates two pairs of complemented center based
PWM signals.
DMA Data Access N/A
DMA Channels N/A
DMA Chaining N/A
Boot Capable N/A
Local Memory No
Clock Operation f
PCLK
Table 7-1. PWM Specifications (Cont’d)
Feature Availability
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