ADSP-214xx SHARC Processor Hardware Reference 3-123
External Port
4. If circular buffering is needed, use the corresponding TCB storage.
5. Enable DMA using the
DMAEN, bit, set chaining using the CHEN bit.
If circular buffering is required, set the CBEN bit in the DMACx regis-
ters. It is advised that programs flush the DMA FIFOs using the
DFLSH bit when DMA is enabled.
Once the DMA control register is initialized, the DMA controller fetches
the DMA descriptors from the address pointed to by the external port
chain pointer register (CPEP).
Once the DMA descriptors are fetched, the normal DMA process starts.
Upon completion, new DMA descriptors are loaded and the process is
repeated until CPEP = 0x0. A DMA completion interrupt is generated at
the end of each DMA block or at the end of an entire chained DMA,
depending on the PCI bit setting.
Delay Line DMA
1. Configure the AMICTLx register with the desired wait states, enable
AMI, data bus width and other parameters.
2. Initialize the CPEP register and set the PCI bit if interrupts are
required after the end of each delay line DMA block.
3. Enable DMA (
DMAEN), delay line DMA (DLEN), chaining (CHEN) if
required in the DMACx register. Programs should flush the DMA
FIFO (
DFLSH) along with enabling the DMA. If circular buffering
is required (which is normally the case) enable it by setting the
CBEN bit.
Once the DMA control register is initialized the DMA engine fetches the
DMA descriptors from the address pointed to by the
CPEP register. Once
the delay line DMA access is complete, the new DMA descriptors are
loaded and the process is repeated until
CPEP = 0x0. A DMA completion
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