ADSP-214xx SHARC Processor Hardware Reference 3-81
External Port
DDR2 access occurs and the DDR2 exits from self-refresh mode.
The minimum time between a subsequent self-refresh entry and
exit command is the t
RAS
cycle. If a self-refresh request is issued
during any external port DMA, the DDR2 controller grants the
request with the t
RAS
cycle and continues DMA operation
afterwards.
Single-Ended Data Strobe
DDR2 data strobe mode is specified for either single ended or differential
mode, depending on the setting of the EMR register enable DDR2_DQS
mode bit. The timing advantages of differential mode are realized in sys-
tem design.
The method by which the DDR2 pin timing is measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to
the rising or falling edges of DDR2_DQS crossing at VREF. In differential
mode, these timing relationships are measured relative to the crosspoint of
DDR2_DQSS and its complement, DDR2_DQS. This distinction in timing
methods is guaranteed by design and characterization. When differential
data strobe mode is disabled via the EMR register, the complementary pin,
DDR2_DQS, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor
to insure proper operation.
On Die Termination (ODT)
The DDR2 controller contains a separate pin (DDR2_ODT) that controls
on-die termination. By default this pin is deasserted. If during power-up,
the ODT register field in the DDR2CTL3 register is programmed with any Rtt
value, the
ODT pin is asserted after the power-up sequence has finished.
The level can be changed by forcing another power-up sequence which
disables Rtt resistance in the
ODT field. After completion, the ODT pin is
deasserted. Note that the
ODT pin control is independent on the DDR2
data access directions (read or write).
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