DDR2 DRAM Controller (ADSP-2146x)
3-48 ADSP-214xx SHARC Processor Hardware Reference
• Supports dual data instruction type 1
• Parallel access between DDR2 and AMI possible (no multiplexed
pins)
Pin Descriptions
The pins used by the external memory interface are described in the
ADSP-2146x SHARC Processor Data Sheet. Additional information on pin
multiplexing can be found in “Pin Descriptions” on page 23-2.
Functional Description
On SDRAM systems all timing is referenced to the rising edge of the clock
as per the JEDEC specification. However, since the clock speed has
increased this approach becomes limited based on setup and hold times.
DDR2 is no longer system synchronous (as SDRAM), it is source syn-
chronous which means the data source provides a reference signal (called
the data strobe signal or DQS) which is sampled by the receiver and used to
latch the data accordingly.
Therefore, the architecture is enhanced into three blocks in order to fulfill
the high speed constraints. One block is the DDR2 controller which inter-
faces to the core or DMA containing the state machine to provide the
various commands to the DDR2 memory. Another block is the important
DDR2 DLL circuit connected to the DDR2 controller and the final block
contains the data capture (I/O pads).
The DDR2 DLL acts as an on-chip interface between the on-chip DDR2
controller and the off-chip DDR2 DRAM to meet the timing require-
ments of either block. Figure 3-11 is a representation of part a system and
shows the interaction of the DDR2 DLL with the controller and the exter-
nal memory. There is one DDR2 DLL1–0 block for every set of 8 bits of
data (DDR2_DATA), data strobe (DDR2_DQS), and data mask (DDR2_DM).
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