ADSP-214xx SHARC Processor Hardware Reference 6-21
FFT/FIR/IIR Hardware Modules
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
FFT Accelerator Effect Latency
After the FFT registers are configured the effect latency is 1.5 PCLK cycles
minimum and 2 PCLK cycles maximum. Writes to the PMCTL1 register have
an effect latency of two PCLK cycles. Wait for at least four CCLK cycles after
selecting an accelerator before accessing any of its registers.
Programming Model
There are two separate programming models, one for a FFT that fits in the
accelerator’s internal memory (N = 256 points or less) and one for a FFT
that is larger than the accelerator’s internal memory (N = 512 points or
more). In both models, is assumed that the accelerator starts in idle mode.
N <= 256, No Repeat
For details on the storage format of the coefficients see “Internal Memory
Storage” on page 6-8.
1. Configure the ACCSEL bits in the PMCTL1 register to select the FFT
accelerator.
2. Program the FFTCTL2 register with:
VDIM = N/16
LOG2VDIM = Log2(N)
HDIM = 0
To Next Page
Loading...
Need help?
General
