Functional Description
7-14 ADSP-214xx SHARC Processor Hardware Reference
required, provided the change is done a few cycles before the next period
change.
Complementary Outputs
The PWM controller can be operatde in paired or non paired mode
(
PWMCTLx register).
In non paired mode (default) both outputs (high and low side) are driven
independently. Since paired mode drives the output logic of the PWM in
a complementary fashion (low side = /high side), this feature may be use-
ful in PWM bridge applications.
Crossover
The PWMSEG3–0 registers contain two bits (AHAL_XOVR and BHBL_XOVR), one
for each PWM output. If crossover mode is enabled for any pair of PWM
signals, the high-side PWM signal from the timing unit (for example, AH)
is diverted to the associated low side output of the output control unit so
that the signal ultimately appears at the AL pin.
The corresponding low side output of the timing unit is also diverted to
the complementary high side output of the output control unit so that the
signal appears at the AH pin. Following a reset, the two crossover bits are
cleared so that the crossover mode is disabled on both pairs of PWM sig-
nals. Even though crossover is considered an output control feature, dead
time insertion occurs after crossover transitions to eliminate
shoot-through safety issues.
Note that crossover mode does not work if:
1. One signal of
PWM_AL–PWM_AH or PWM_BL–PWM_BH is disabled.
2. PWM_AL and PWM_AH or PWM_BL and PWM_BH have different polarity
settings from
PWMPOLx registers.
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