ADSP-214xx SHARC Processor Hardware Reference 21-1
21 TWO WIRE INTERFACE
CONTROLLER
The two wire interface (TWI) controller allows a device to interface to an
inter-IC bus as specified by Philips. The TWI is fully compatible with the
widely used I
2
C bus standard. It is designed with a high level of function-
ality and is compatible with multi-master, multi-slave bus configurations.
To preserve processor bandwidth, the TWI controller can be set up with
transfer initiated interrupts to service FIFO buffer data reads and writes
only. Protocol related interrupts are optional.The TWI specifications are
shown in Table 21-1.
Table 21-1. TWI Specifications
Feature Availability
Connectivity
Multiplexed Pinout No
SRU DAI Required No
SRU DAI Default Routing N/A
SRU2 DPI Required Yes
SRU2 DPI Default Routing Yes
Interrupt Control Yes
Protocol
Master Capable Yes
Slave Capable Yes
Transmission Simplex
Transmission Half Duplex
Transmission Full Duplex
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