ADSP-214xx SHARC Processor Hardware Reference 10-45
Serial Ports
Each transmitter and receiver has its own DMA registers. The same DMA
channel drives the left and right I
2
S channels for the transmitter or the
receiver. The software application must stop multiplexing the left and
right channel data received by the receive buffer, because the left and right
data are interleaved in the DMA buffers.
Channel A and B on each SPORT share a common interrupt vector. The
DMA controller generates an interrupt at the end of DMA transfer only.
Figure 10-5 on page 10-28 shows the relationship between frame sync
(word select), serial clock, and I
2
S data. Timing for word select is the same
as for frame sync.
The value of the SPTRAN bit in SPCTLx (0 = RX, 1 = TX) determines whether
the receive or transmit register for the SPORT becomes active.
The SPORT DMA channels are assigned higher priority than all other
DMA channels (for example, the SPI port) because of their relatively low
service rate and their inability to hold off incoming data. Having higher
priority causes the SPORT DMA transfers to be performed first when
multiple DMA requests occur in the same cycle. The serial port DMA
channels are numbered and prioritized as shown in Table 2-28 on
page 2-36.
Although the DMA transfers are performed with 32-bit words, serial ports
can handle word sizes from 3 to 32 bits, with 8 to 32 bits for I
2
S mode. If
serial words are 16 bits or smaller, they can be packed into 32-bit words
for each DMA transfer. DMA transfers are configured using the
PACK bit
in the SPCTLx registers. When serial port data packing is enabled (PACK =
1), the transmit and receive interrupts are generated for the 32-bit packed
words, not for each 16-bit word.
External Memory DMA Transfers
In previous SHARC processors, transferring data from a SPORT to exter-
nal memory required placing that data temporarily in internal memory
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