ADSP-214xx SHARC Processor Hardware Reference 15-19
Serial Peripheral Interface Ports
in the registers are zeros. This code works only if the
MSBF bit is zero in
both the transmitter and receiver, and the SPICLK frequency is less. If MSBF
= 1 in the transmitter and receiver, and SPICLK has a lower frequency, the
received words follow the order 0x12, 0x34, 0x56, 0x78.
16-bit word. When transmitting, the SPI port sends out only the lower 16
bits of the word written to the SPI buffer. When receiving, the SPI port
packs the 16-bit word to the lower 32 bits of the RXSPI buffer while the
upper bits in the register are zeros.
32-bit word. No packing of the RXSPI or TXSPI registers is necessary as the
entire 32-bit register is used for the data word.
Core Buffer Status
For core access to SPI, master and slave mode operates different:
1. If core access to a SPI slave is unable to keep up with the trans-
mit/receive stream during a transfer operation (because of an
interrupt or any other reason) the SPI operates according to the
states of the SENDZ and GM bits in the SPICTLx register.
•If SENDZ = 1 and the transmit buffer is empty, the device
repeatedly transmits zeros on the MOSI pin. One word is
transmitted for each new transfer initiate command.
•If
SENDZ = 0 and the transmit buffer is empty, the device
repeatedly transmits the last word transmitted before the
transmit buffer became empty.
•If GM = 1 and the receive buffer is full, the device continues
to receive new data from the MISO pin, overwriting the older
data in the
RXSPI buffer.
To Next Page
Loading...
Need help?
General
