Interrupts
20-14 ADSP-214xx SHARC Processor Hardware Reference
UARTRXCTL registers) and enabling DMA using the UARTDEN bits. A DMA
can be interrupted by resetting the UARTDEN bit in the control register. A
DMA request that is already in the pipeline completes normally.
DMA Chaining
DMA chaining is enabled by setting the UARTCHEN bit in the transmit and
receive control registers. When chaining is enabled at the end of a current
DMA, the next set of DMA parameters are loaded from internal memory
and a new DMA starts. The index of the memory location is written in the
chain pointer register. DMA parameter values reside in consecutive mem-
ory locations as shown in Table 2-16 on page 2-15. Chaining ends when
the chain pointer register contains address 0x00000 for the next parameter
block.
Interrupts
The following sections provide information on the UART and interrupt
generation. Table 20-4 provides an overview of UART interrupts.
If UART core interrupts (core RX INT of UART ) are routed via
the DPI interrupt, programs do not need to read the DPI_IRPTL
register for interrupt acknowledge. Reading the UARTIIR register
also clears the
DPI_IRPTL register.
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