Processor Booting
23-12 ADSP-214xx SHARC Processor Hardware Reference
SPI Port Booting
The SHARC processors support booting from a host processor using SPI
slave mode or booting from an SPI flash, SPI PROM, or a host processor
via SPI master mode. Both SPI boot modes (master and slave) support 8-,
16-, or 32-bit SPI devices. For bit settings, see the product specific proces-
sor data sheet.
In both (master and slave) boot modes, the LSBF format is used
and SPI mode 3 is selected (clock polarity and clock phase = 1).
Both SPI boot modes use default routing with the DPI pin buffers
For more information, see “DPI Default Routing” on page 9-31.
Master Boot Mode
In master boot mode, the processor initiates the booting operation by:
1. Activating the SPICLK signal and asserting the SPI_FLG0_O signal to
the active low state.
2. Writing the read command 0x03 and address 0x00 to the slave
device as shown in Figure 23-5.
Master boot mode is used when the processor is booting from an
SPI-compatible serial PROM, serial FLASH, or slave host processor. The
specifics of booting from these devices are discussed individually.
SPI master booting uses the default bit settings shown in Table 23-7.
Table 23-6. SPIDMAC Master/Slave Boot Settings (0x7)
Bit Setting Comment
SPIDEN Set (= 1) SPI DMA
SPIRCV Set (= 1) SPI receive
INTEN Set (= 1) SPI interrupt
SPICHEN Cleared (= 0) SPI DMA chaining
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