ADSP-214xx SHARC Processor Hardware Reference 2-49
I/O Processor
Debug Features
The JTAG interface provides some user debug features for DMA in that it
allows programs to place breakpoints on the IOD buses. Programmers can
then insert DMA related breakpoints. For more information, see the Visu-
alDSP tools documentation and the SHARC Processor Programming
Reference.
Emulation Considerations
An emulation halt will optionally stop the DMA engine. The JTAG inter-
face provides some user debug features for DMA. Placing breakpoints on
the IOD address buses allows DMA related breakpoints. For more infor-
mation, see the VisualDSP tools documentation and the SHARC Processor
Programming Reference.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
IOP Effect Latency
Table 2-30 lists the time required to load a specific TCB from the internal
memory into the DMA controller. During this time, both buses (for a
peripheral DMA, the IOD0 bus and for external port DMA the IOD1
bus) are locked and cannot be interrupted.
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