ADSP-214xx SHARC Processor Hardware Reference 2-29
I/O Processor
The peripheral’s DMA controller tracks status information of the channels
in each of the peripheral registers (for example
SPMCTLx, SPIDMACx,
DAI_STAT, DMACx, and MTMCTL).
• DMA channel status (status bit is set until the DMA terminates)
• TCB chain loading status (status bit is set until TCB loading
completes)
If polling the status of a chained DMA, the DMA status bit is first set
when the TCB has terminated, then it is cleared. The TCB status loading
bit is set until the load is finished and cleared on load completion. This
procedure is repeated for all subsequent DMA blocks.
Note that polling the DMA status registers (especially chained DMA)
reduces I/O bandwidth.
DMA Start and Stop Conditions
The difference between single DMA and chained DMA is based on the
auto-linkage process where the DMA’s attributes are stored in internal
memory and automatically loaded by the IOP if requested.
A DMA sequence starts when one of the following occurs.
• Chaining is disabled, and the DMA enable bit transitions from low
to high.
• Chaining is enabled, DMA is enabled, and the chain pointer regis-
ter address field is written with a non zero value. In this case, TCB
chain loading of the channel parameter registers occurs first.
• Chaining is enabled, the chain pointer register address field is non-
zero, and the current DMA sequence finishes. Again, TCB chain
loading occurs.
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