DDR2 DRAM Controller (ADSP-2146x)
3-68 ADSP-214xx SHARC Processor Hardware Reference
t
RAS
= 9 cycles
t
RP
= 3 cycles
The equation for RDIV yields:
RDIV = (200 × 10
6
× 7.8 × 10
–6
) – (9 + 3) = 1548 clock cycles.
This means RDIV is 0x614 and the DDR2RRC register bits 13–0 should be
written with 0x60C.
Note that the RDIV bit must be programmed to a non-zero value if the
DDR2 controller is enabled. When RDIV = 0, operation of the controller is
not supported and can produce undesirable behavior. Values for RDIV can
range from 0x001 to 0x3FFF.
Data Mask
The DDR2 controller provides two DDR2_DM1-0 pins. Both pins (for each
byte) should be connected to the DDR2 DM pins.
The meaning of this pin is significant, based on the fact that the minimum
burst length is 4 and a burst is not divisible. The DDR2_DM1-0 pins are used
to mask the data on both edges of the DQS signal during writes in cases less
than 4 sequential writes, for example a single write need to mask the data
for the next sequential 3 writes.
The DDR2_DM1-0 pins are useful for performance monitoring during
write commands. Every time these signals are asserted indicates the
controller masks unwanted data writes causing performance penal-
ties. For reads, the controller simply does not latch the data from
the burst.
Resetting the Controller
Like any other peripheral, the DDR2 controller can be reset by hard- or a
soft reset. Both reset modes pull the DDR2_CKE pin asynchronously low.
Since DDR2_CKE drops asynchronously and the PLL goes into bypass mode
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