Clocking AMI/DDR2
3-6 ADSP-214xx SHARC Processor Hardware Reference
The SDRAM clock ratio settings are independent from the periph-
eral clock (PCLK).
To obtain certain higher SDRAM frequencies, the core frequency
may need to be reduced.
Clocking AMI/DDR2
The fundamental timing clock of the external port is DDR2 clock
(DDR2_CLK). The AMI/DDR2 controller is capable of running up to core
clock/2 speed (CCLK/2) and can run at various frequencies, depending on
the programmed DDR2 clock (
DDR2_CLK) to core clock (CCLK) ratios. For
information processor instruction rates, see the appropriate processor data
sheet.
The DDR2 clock ratio settings are independent from the periph-
eral clock (
PCLK).
Table 3-2. External Port Clock Frequencies
CCLK:SDCLK
Clock Ratio
CCLK = 400
MHz
CCLK = 333
MHz
CCLK = 266
MHz
CCLK = 200
MHz
1:2.0 N/A 166 133 100
1:2.5 160 133 106 80
1:3.0 133 111 88 67
1:3.5 114 95 76 57
1:4.0 100 83 66 25
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