Functional Description
9-16 ADSP-214xx SHARC Processor Hardware Reference
behave as documented in Chapter 10, Serial Ports. The SRU then
becomes transparent to the peripheral. Figure 9-8 demonstrates
SPORT0 properly routed to DAI pins 1 through 4; although it can
be equally well routed to any of the 20 DAI pins.
The pin buffer output enable signals (
x_PBEN_O) supported by any
peripheral should always be routed to the dedicated pin buffer
enable input (DAI_PBEN_I, DPI_PBEN_I).
Output Signals Without Pin Buffer Enable Control
Some peripherals have signal outputs without automated pin buffer con-
trol enable (PDAP_STRB_O, MISCx_O, BLK_START_O).
The operation of these peripherals is simplified as the routing to a
DAI/DPI pin buffer enable input requires a static high from the SRU. In
order to disable the pin buffer output, software must clear the pin buffer
enable input accordingly.
Signal Routing Units (SRUs)
The following sections provide more detail specific to the SRUs.
Signal Routing Matrix by Groups
The SRU can be likened to a set of patch bays, which contains a bank of
inputs and a bank of outputs. For each input, there is a set of permissible
output options. Outputs can feed to any number of inputs in parallel, but
every input must be patched to exactly one valid output source. Together,
the set of inputs and outputs are called a group. The signal’s inputs and
outputs that comprise each group all serve similar purposes. They are
compatible such that almost any output-to-input patch makes functional
sense. With the grouping, the multiplexing scheme becomes highly effi-
cient since it wouldn't make sense for instance to route a frame sync signal
to a data signal.
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