Programming Model
15-32 ADSP-214xx SHARC Processor Hardware Reference
Slave Mode Transfers
When the SPI is configured as a master, regardless of core or DMA the
SPI ports should be configured and transfers started using the following
steps.
1. Route all required signals (
MOSI, MISO, SPICLK) for slave mode
including the
SPI_DS_I as slave select input.
2. Write to the SPICTLx and keep the (SPIMS) cleared, enabling the
device as a slave and configuring the SPI system by specifying the
appropriate word length, transfer format and other necessary infor-
mation. For DMA operation set TIMOD = 10.
The next steps are dependant on whether the access is a core or a DMA
access.
Core Slave Transfers
The following steps illustrate SPI operation in slave mode.
1. Write the data to be transmitted into the TXSPIx buffer to prepare
for the data transfer.
2. When a device is enabled as a slave, the start of a transfer is trig-
gered by a transition of the SPI_DS_I select signal to the active state
(low) or by the first active edge of the clock (SPICLK), depending on
the state of CPHASE.
3. The reception or transmission continues until
SPI_DS_I is released
or until the slave has received the proper number of clock cycles.
4. The slave device continues to receive or transmit with each new
falling-edge transition on SPI_DS_I or active SPICLK clock edge.
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