ADSP-214xx SHARC Processor Hardware Reference A-41
Registers Reference
DLL1 Control Register 1 (DLL1CTL1)
The
DLL1CTL1 register shown in Figure A-17 and described in Table A-21
includes the programmable parameters associated with the DLL1 device.
Note that it takes at least 9 core clock cycles to perform a DLL reset.
Table A-20. DLL0CTL1 Register Bit Descriptions (RW)
Bit Name Description
8–0 Reserved
9 RESETDLL Reset DLL Control Logic. Active high, when active, it resets the
DLL control logic only, including the 90 degree DQS shifters.
0 = No effect
1 = Reset DLL0 control logic
10 RESETDAT Reset Data Capture Logic. Active high, when active, it resets the
data capture logic only, including P and N buffers.
0 = No effect
1 = Reset DLL0 data capturel logic
11 RESETCAL Reset DQS Phase Calibration Logic. Active high, when active, it
resets the DQS phase calibration logic.
0 = No effect
1 = Reset DLL0 DQS phase calibration logic
31–12 Reserved
Figure A-17. DLL1CTL1 Register
RESETDLL
RESETDAT
Reset Data Capture Logic
Reset DLL Control Logic
31 302928 27 26 25 24 23 22 21 20 19 18 17 16
09 837564 2114 12 11 101315
RESETCAL
Reset the DQS Phase Cali-
bration Logic
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