Operation Modes
10-26 ADSP-214xx SHARC Processor Hardware Reference
Clocking Options
In standard serial mode, the serial ports can either accept an external serial
clock or generate it internally. The
ICLK bit in the SPCTL register deter-
mines the selection of these options. For internally-generated serial clocks,
the CLKDIV bits in the DIVx register configure the serial clock rate.
Finally, programs can select whether the serial clock edge is used for sam-
pling or driving serial data and/or frame syncs. This selection is performed
using the CKRE bit in the SPCTL register.
Frame Sync Options
This section describes the different options for frame sync in standard
serial mode.
Framed Versus Unframed Frame Syncs
The use of frame sync signals is optional in serial port communications.
The FSR (transmit frame sync required) bit determines whether frame sync
signals are required. Active low or active high frame syncs are selected
using the LFS bit. This bit is located in the SPCTLx control registers.
When FSR is set (=1), a frame sync signal is required for every data word.
To allow continuous transmission from the processor, each new data word
must be loaded into the transmit buffer before the previous word is shifted
out and transmitted.
When
FSR is cleared (=0), the corresponding frame sync signal is not
required. A single frame sync is required to initiate communications but it
is ignored after the first bit is transferred. Data words are then transferred
continuously in what is referred to as an unframed mode.
When DMA is enabled in a mode where frame syncs are not
required, DMA requests may be held off by chaining or may not be
serviced frequently enough to guarantee continuous unframed data
flow.
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