Effect Latency
9-42 ADSP-214xx SHARC Processor Hardware Reference
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Signal Routing Unit Effect Latency
After the DAI/DPI registers are configured the effect latency is 2 PCLK
cycles minimum and 3 PCLK cycles maximum.
Programming Model
As discussed in the previous sections, the signal routing unit is controlled
by writing values that correspond to signal sources into bit fields that fur-
ther correspond to signal inputs. The SRU is arranged into functional
groups such that the registers that are made up of these bit fields accept a
common set of source signal values.
In order to ease the coding process, the header file
SRU.H is included with
the VisualDSP++ tools. This file implements a macro that abstracts away
most of the work of signal assignments and functions. The macro has
identical syntax in C/C++ and assembly, and makes a single connection
from an output to an input as shown below.
SRU(Output Signal, Input Signal);
The names passed to the macro are the names given “DAI Signal Routing
Unit Registers” on page A-118.
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