Debug Features
21-18 ADSP-214xx SHARC Processor Hardware Reference
IMASK or LIRPTL registers must also be configured based on the program-
mable interrupt to be used. The ISR needs to clear the status bits of the
TWIIRPTL register by explicitly writing 1 into the status bit (W1C) as
shown in Listing 21-3.
Listing 21-3.
TWI_ISR:
ustat1 = dm(TWIIRPTL);
bit set ustat1 TWITXINT;
dm(TWIIRPTL) = ustat1; /* W1C to clear TWI TX interrupt */
instruction;
instruction;
rti;
Debug Features
The following section provides information on debugging features avail-
able with the TWI.
Buffer Hang Disable
To support debugging buffer transfers, the processors have a buffer hang
disable (
BHD) bit in the TWIFIFOCTL register. When set (=1), this bit pre-
vents the processor core from detecting a buffer-related stall condition,
permitting debugging of this type of stall condition. For more informa-
tion, see “Buffer Hang Disable (BHD)” on page 10-54.
Loop Back Routing
The controller supports an internal loop back mode by using the SRU.
For more information, see “Loop Back Routing” on page 9-40.
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