Programming Model
15-38 ADSP-214xx SHARC Processor Hardware Reference
With SPI enabled:
1. Disable DMA and clear the DMA FIFO by
FIFOFLSH bit in the
SPIDMACx register. This ensures that any data from a previous DMA
operation is cleared before configuring a new DMA operation.
2. Clear the RXSPIx/TXSPIx registers and the buffer status without dis-
abling SPI. This can be done by ORing 0xC0000 with the present
value in the SPICTLx registers. Use the RXFLSH and TXFLSH bits to
clear the RXSPIx/TXSPIx registers and the buffer status.
3. Clear all errors by writing to the W1C-type bits in the SPISTAT
register. This ensures that error bits SPIOVF and SPIUNF in the
SPIDMACx registers are cleared when a new DMA is configured.
4. Reconfigure the SPICTL register to remove the clear condition on
the RXSPI/TXSPI register bits.
5. Configure DMA by writing to the DMA parameter registers and
the SPIDMACx register.
Multi-Master Transfers
The following steps show how to implement a system with two SPI
devices. Since the slaves cannot initiate transfers over the bus, the master
must send frames over the
MOSI pin. This ensures that slaves can respond
to the bus by sending messages over the MISO pin to the bus master.
1. Slave writes message to its
MISO pin.
2. Slave starts polling its SPI_DS_I pin which is currently low.
3. Message is latched by current master and decoded.
4. Master deasserts the slave select signal and clears the
SPIMS bit to
become a slave.
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