Analog Devices SHARC ADSP-214 Series - Interrupt Routing; DPI; TWI

Interrupts
21-16 ADSP-214xx SHARC Processor Hardware Reference
Interrupt Routing
The following sections describe the various possibilities for routing a TWI
interrupt to the interrupt vector table (IVT).
DPI
The TWI interrupt is combined into the digital peripheral interface (DPI)
interrupt. The DPI_IRPTL register determines whether an interrupt is gen-
erated. Listing 21-1 shows an example of how to enable the TWI over the
DPI.
Listing 21-1. Enabling DPI TWI Interrupts
bit set mode1 IRPTEN; /* enables global interrupts */
bit set imask DPII; /* unmasks DPI interrupt */|
ustat1 = TWI_INT;
dm(DPI_IRPTL_RE) = ustat1; /* unmasks TWI interrupt */
TWI
The TWI receive and transmit interrupts can also be programmed
through the peripheral interrupt control registers (PICRx) as separate inter-
Table 21-4. TWI Interrupt Overview
Interrupt
Source
Interrupt Condition Interrupt
Completion
Interrupt
Acknowledge
Default IVT
DPI TWI
(TX/RX)
– Master (TX completion, TX/RX
buffer service, error)
– slave (initiative, completion,
overflow, error)
Internal transfer
completion
W1C (Write one
to clear) TWI-
IRPTL register +
RTI instruction
P14I
TWI(TX/RX) – Master (TX completion, TX/RX
buffer service, error)
– slave (initiative, completion,
overflow, error)
Internal transfer
completion
W1C (Write one
to clear) TWI-
IRPTL register +
RTI instruction
Need to route
TWII (PICRx)
to any PxxI
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