ADSP-214xx SHARC Processor Hardware Reference 19-3
WatchDog Timer – ADSP-2147x
• Programmable trip counter which allows programs to set the num-
ber of times the WDT can expire before the
WDTRSTO signal is
asserted continuously.
• WDT space is locked and can be accessed only after unlocking the
space using commands.
Pin Descriptions
The pins used for the watchdog timer are described in the ADSP-2147x
data sheet.
Register Overview
The following sections provide brief descriptions of the primary registers
used to program the timers. For more information, see “Peripheral Timer
Registers” on page A-269.
Control Register (WDTCTL). The control register is a 32-bit system
memory-mapped register used to configure the watchdog timer. Any
writes made by the Software to the Register will keep it enabled. Only an
External Hardware Reset can disable WDT.
Count Register (WDTCNT). Holds the 32-bit unsigned count value.
The WDTCNT register must always be accessed with 32-bit read/writes.
Current Count Status Register (WDTCURCNT). Contains the current
count value of the watchdog timer. Reads to WDTCURCNT return the
current count value.
Status Register (WDTSTATUS). Contains the watchdog timer status
information. This register is not cleared by the WDT generated reset.
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