Phase-Locked Loop (PLL)
22-6 ADSP-214xx SHARC Processor Hardware Reference
If the
DIVEN bit is set, new post divider ratios are picked up on the fly and
the clocks smoothly transition to their new values within 14 core clock
(CCLK) cycles.
Post divider ratio changes (PLLD bits) do not require bypass mode.
The output clock generator block also controls bypass mode. For a
description of the PMCTL bits, see “ADSP-2146x Power Management Reg-
isters” on page A-6 and “ADSP-2147x/ADSP-2148x Power Management
Registers” on page A-12.
Core Clock (CCLK)
The PLLD bits define the VCO output clock to core clock ratio to build the
processor core clock (CCLK). The post divider can be changed any time and
new division ratios are implemented on the fly.
IOP Clock (PCLK)
The peripheral clock is derived from the core clock with a fixed post divi-
sor of 2. This clock is the master clock for all peripherals (except SDRAM)
including the I/O processor (IOP).
SDRAM/DDR2 Clock (SDCLKx/DDR2_CLK)
The DDR2/ SDRAM clock is derived from the core clock. The default
divisor is 2. After
RESET is deasserted, both DDR2/SDRAM output clocks
are driven with
CCLK/2 = PCLK, independent of the DDR2/SDRAM con-
troller configuration. Note that the DIVEN bit needs to be changed
whenever there is a change from the default ratio.
Default PLL Hardware Settings
Table 22-2 demonstrates the internal core clock switching frequency
across a range of
CLKIN frequencies. The minimum operational range for
any given frequency may be constrained by the operating range of the
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