ADSP-214xx SHARC Processor Hardware Reference 3-53
External Port
6. Bit 10 – Differential
DDR2_DQS enable/disable
7. Bit 12 – Output buffer enable/disable
8. Bits 15–14 = 01 for EMR1
The command can also be triggered by setting the FEMR bit in the
DDR2CTL0 register.
Load Extended Mode Register 2
Values written into the DDR2CTL4 register are loaded into the EMR2 register
as is during power up.
1. Bits 13–0 = always zero
2. Bits 15–14 = 10 for EMR2
Load Extended Mode Register 3
Values written into the DDR2CTL5 register are loaded into the EMR3 register
during power up.
1. Bits 13–0 = always zero (OCD exit)
2. Bits 15–14 = 10 for EMR3
The DDR2 controller does not support off-chip driver (OCD) cal-
ibration. Also note that all mode registers must be programmed
since the default settings in the DDR2 device are not defined.
Bank Activation
This command is required if the next data access is on a different page in
the same internal bank or in a different internal bank that is in an idle
state. The controller executes the pre-charge command, followed by a
bank activate command, to activate the page in the desired DDR2 internal
bank. The controller is able to open up to eight pages at the same time in
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