ADSP-214xx SHARC Processor Hardware Reference 15-11
Serial Peripheral Interface Ports
Multi Master Systems
The SPI does not have an acknowledgement mechanism to confirm the
receipt of data. Without a communication protocol, the SPI master has no
knowledge of whether a slave even exists. Furthermore, the SPI has no
flow control.
Slaves can be thought of as input/output devices of the master. The SPI
does not specify a particular higher-level protocol for bus mastership. In
some applications, a higher-level protocol, such as a command-response
protocol, may be necessary. Note that the master must initiate the frames
for both its’ command and the slave’s response.
Multi master mode allows an SPI system to transfer mastership from one
SPI device to another. In a multi device SPI configuration, several SPI
ports are connected and any one (but only one) of them can become a
master at any given time.
In this configuration, every
MOSI pin in the SPI system is connected. Like-
wise, every
MISO pin in the system is on a single node, and every SPICLK
pin should be connected (see Figure 15-4). SPI transmission and reception
are always enabled simultaneously, unless the broadcast mode has been
selected.
The master’s FLAGx pins connect to each of the slave SPI devices in the sys-
tem via their
SPIDS pins. To enable the different slaves, connect the slave
Figure 15-3. SHARC Processor as SPI Master
DATA
DPI (SPI_CLK_O)
DPI (SPI_FLG0_O)
DPI (SPI_MOSI_O)
CCLK
CLATCH
ADSP-214xx
MASTER DEVICE
a AD1855
STEREO 96 kHz DAC
S
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