ADSP-214xx SHARC Processor Hardware Reference 6-27
FFT/FIR/IIR Hardware Modules
4. Program the
FFTCTL2 register with:
VDIM = V/16
LOG2VDIM = Log2(V)
HDIM = H/16
LOG2HDIM = Log2(H)
NOVER256 = VH/256
FFT_RPT = 1.
5. Program the FFTCTL1 register with:FFT_RST = 0
FFT_EN = 1
FFT_START = 1
FFT_DMAEN = 1
FFT_DEBUG = 0
For steps 6–15, see “N >= 512, No Repeat” above.
Debug Mode
The next sections show the steps required for reading and writing local
memory in debug mode.
Write to Local Memory
1. Enable the FFT module using the PMCTL1 register.
2. Wait at least 4
CCLK cycles.
3. Clear the
FFT_DMAEN bit in the FFTCTL1 register.
4. Set the FFT_DBG bit in the FFTCTL1 register.
5. Write first data to the
FFTDDATA register.
6. Write address to the FFTDADDR register. Note the MSB Address bits
determines which memory to write.
7. Wait at least 12 CCLK cycles before writing again FFTDDATA register.
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