Data Transfers
10-46 ADSP-214xx SHARC Processor Hardware Reference
and then transferring it to external memory using DMA. The
ADSP-214xx processors allow direct DMA transfers between SPORTs
and external memory which removes this overhead, freeing up the core
and internal memory for other peripherals. The SPORT DMA and chain
pointer registers have been expanded to hold the external memory address.
Standard DMA
Each SPORT DMA channel has an enable bit (SDEN_A and SDEN_B) in its
SPCTLx register. When DMA is disabled for a particular channel, the
SPORT generates an interrupt every time it receives a data word or when-
ever there is a vacancy in the transmit buffer. For more information, see
“Single Word Transfers” on page 10-43.
To set up a serial port DMA channel, write a set of memory buffer param-
eters to the SPORT DMA parameter registers as shown in Table 2-14 on
page 2-14.
Load the II, IM, and C registers with a starting address for the buffer, an
address modifier, and a word count, respectively. The register contains the
internal memory address for transfers to internal memory and the external
memory address for transfers to external memory. These registers can be
written from the core processor or from an external processor.
Once serial port DMA is enabled, the processor’s DMA controller auto-
matically transfers received data words in the receive buffer to the buffer
in internal or external memory, depending on the transfer type. Likewise,
when the serial port is ready to transmit data, the DMA controller auto-
matically transfers a word from internal or external memory to the
transmit buffer. The controller continues these transfers until the entire
data buffer is received or transmitted.
When the count register of an active DMA channel reaches zero (0), the
SPORT generates the corresponding interrupt.
To Next Page
Loading...
Need help?
General
